ORT8850-FPSC-EV【PDF 1/2 页】BOARD EVAL ORCA ORT8850 FPSC

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录346

[1页]2页

FIELD PROGRAMMABLE SYSTEM-ON-A-CHIP

ORCA ORT8850

8-Channel High-Speed Serial Backplane Driver

Lattice has developed a solution for designers who need the

many advantages of FPGA-based design implementation,

coupled with high-speed serial backplane data transfer.

Built on the ORCA ? Series 4 reconfigurable embedded

system-on-a-chip (SoC) architecture, the ORT8850 family is

made up of backplane transceivers containing eight

channels, each operating at up to 850 Mbits/s (6.8 Gbits/s

when all eight channels are used) full-duplex synchronous

interface, with built-in clock and data recovery (CDR) in

standard-cell logic, along with up to 600K usable FPGA

system gates.

The ORT8850 family offers a clockless high-speed interface

for inter-device communication, on a board or across a

backplane. The built-in clock recovery of the ORT8850

allows higher system performance, easier- to-design clock

domains in a multiboard system, and fewer signals on the

backplane. Network designers will also benefit from the

backplane transceiver as a network termination device. The

backplane transceiver offers SONET scrambling/

descrambling of data and streamlined SONET framing,

pointer moving, and transport overhead handling, plus the

programmable logic to terminate the network into

proprietary systems. For non-SONET applications, all

SONET functionality is hidden from the user and no prior

networking knowledge is required.

ORCA ORT8850 Block Diagram

Selectable High-Speed Data Rates – 8X 155/212/622/850 Mbits/sec

Low-Power LVDS I/Os

Also included on the device are three full-duplex, high-

speed parallel interfaces, consisting of 8-bit data, control

(such as start-of-cell), and clock. The interface delivers

double data rate (DDR) data at rates up to 311 MHz (622

Mbits/s per pin), and converts this data internal to the

device into 32-bit wide data running at half rate on one

clock edge. Functions such as centering the transmit clock

in the transmit data eye are done automatically by the

interface. Applications delivered by this interface include a

parallel backplane interface similar to the RapidIO packet-

based interface.

High Performance ORCA Series 4 FPGA Gates:

Clock & Data

Recovery

311 MHz

DDR

Interface

311 MHz

DDR

Interface

311 MHz

DDR

Interface

Key Features and Benefits

■

Byte-

Wide

Pseudo-SONET

Framer

Byte-

Wide

Data

? Internal performance of > 250 MHz.

? Up to 600K usable system gates (with ORT8850H).

? 1.5 V operation (30% less power than 1.8 V operation)

? Comprehensive I/O selections including LVTTL,

LVCMOS, GTL, GTL+, PECL, SSTL3/2, HSTL, ZBT,

DDR, LVDS, bused-LVDS, and LVPECL.

ORCA Series 4 FPGA

Up to 600K Gates

User-Configurable I/Os

■

Ease of Design

? Supported by ORCA Foundry 2001 design software

? Complete ORT8850 design kit supplies simulation

models for embedded core, configuration tool, and

integrates with ORCA Foundry 2001

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式